Architecture
Up to three compute tiles, one control core, one memory, one bus. Here's the chip design from a bird's-eye view.
Vexon-1 — Block Diagram
RISC-V controls · Multi-tile computes in parallel · On-chip KV-Cache holds language-model state · On-chip bus connects everything.
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Three tiles compute at the same time – up to three are validated in parallel in hardware today. Stylized: data reaches the tiles via AXI4 and the on-chip bus; the RISC-V core controls the sequence.
Select a layer to learn more.
Output-stationary dataflow
Vexon-1 uses an output-stationary systolic array: weights and activations are fed (broadcast) into the compute grid while partial results stay in place — without a classic adder tree. This sets the architecture apart from weight-stationary designs and is tailored to the math of modern transformers.
How the five innovations work
Explained conceptually — what each innovation does and the benefit it brings. The implementation details remain under NDA.
Sparse Engine — skipping zeros
Function
Detects null operands before computing and skips the multiplication entirely — at up to around 90% sparsity.
Benefit
Less energy and latency for an identical result.
Adaptive Precision — as precise as needed
Function
Switches autonomously between INT4, INT8 and INT16 (with hysteresis), depending on how much precision the data currently needs.
Benefit
More throughput per clock cycle without giving up accuracy.
Hardware Attention — transformer core in hardware
Function
The attention mechanism including softmax runs as a dedicated hardware state machine; null scores are filtered out (sparse-attention fusion).
Benefit
The most compute-intensive part of modern language models runs directly in hardware.
Hardware KV-Cache — memory on-chip
Function
The language-model state (keys and values) lives directly on the chip instead of in slow external memory. Verified bit-exact on both FPGA platforms.
Benefit
No DRAM round-trip, no cloud needed — fast, local inference.
Multi-Tile — parallel instead of serial
Function
Several compute tiles work at the same time. Validated in hardware on the FPGA with up to three tiles, each bit-exact. The tile count is an RTL parameter.
Benefit
The tile count can be adapted to the target size of the chip.
Verification stack
From Verilog RTL through simulation tests, FPGA build, driver, REST API, all the way to the React frontend demo — the entire stack is developed in-house and reproducible.
Deeper architecture under NDA
Full technical specification, FSM details, RTL architecture — available on request for qualified license partners.