Research & Development
From our first software product to our own NPU design — seven phases, and why each follows from the one before.
The story has no versions, no pivots without reason — just a technical logic. Here are the seven phases we went through.
The Question
NeuroVexon began with a simple observation: between powerful AI and data sovereignty, a compromise is expected. We wanted to show it works without that compromise.
Software phase
We first developed modular AI software that runs entirely on local infrastructure — GDPR-compliant, no cloud dependency. This phase brought us to the limit: sovereign AI works at the software layer, but trust in the hardware is the real weakness.
The first FPGA prototypes
We began prototyping our own NPU architectures on FPGA boards. The early experiments turned into a serious engineering discipline: 21 hardware modules, ~4,000 lines of Verilog, more than 10,000 simulation checks passed.
Proof of Concept
On a Xilinx Kria KV260 board we verified five core innovations directly in hardware: Sparse Engine, Adaptive Precision, Multi-Tile parallelism, hardware attention, hardware KV-Cache. Nine of nine tests reproducible via REST API.
The Pivot
With this proof of concept it became clear: sovereign AI doesn't start in software, it starts at the silicon. Whoever controls the chip controls the data. NeuroVexon has been a chip designer since.
Today
Vexon-1 is verified in hardware — on two FPGA platforms, with up to three tiles in parallel, our own RISC-V sequencer and our own Linux image. Three utility models registered with the DPMA. ASIC stage in preparation.
The Dream
Our long-term goal is our own Agentic AI Assistant that runs entirely on NeuroVexon hardware — local on the device, no cloud, no data leaving. Vexon-1 is the foundation. From the software phase we know what a sovereign AI stack must do; from the chip engineering we build the foundation. We don't say exactly when — but that's the direction NeuroVexon is heading.
What happens to the software
The original software modules — Assistant, Desk, Data Layer, Warden, Security Access, Vaxon — are currently not actively developed. The experience gained in this phase about sovereign AI architectures flows entirely into our chip design. We're considering an open-source release of the modules as a contribution to the European AI sovereignty community.
"The path from software vendor to chip designer is not a pivot — it's a logical consequence. Whoever takes AI sovereignty seriously must start at the hardware."