What's happening at NeuroVexon — conference appearances, IP filings, technical milestones.
August 2026 · Böblingen, Germany
It has been quiet around NeuroVexon for a few weeks — because we were building. Vexon-1 now runs on a second, larger FPGA development platform. And for the first time not as a single NPU core, but as a cluster: several compute tiles in parallel on one FPGA, each bit-exact against our reference model.
On top of that: a compute array twice the size per tile, our own RISC-V control core that turns new operations into firmware instead of hardware changes, and our own Linux image with our own driver stack. All five core innovations are proven in hardware through the real driver path. End to end, the NPU computes a typical matrix multiplication 4.6× faster than all four CPU cores of the same chip combined — realistically two to three times against a hand-optimised library.
Why it matters: anyone deploying or licensing edge AI hardware wants to know whether a design scales — from a small sensor to a production line. Our answer is not a promise. It is a measurement. The next step is silicon.
Update video “From one core to a cluster” (approx. 90 seconds).
1 July 2026 · Main Stage, Messe Berlin
NeuroVexon was among the finalists of the Supernova Pitch Competition at GITEX Europe 2026 in Berlin — Europe's largest tech, startup and investment event. On 1 July 2026 we presented Vexon-1 on the Main Stage in front of an international jury and audience, placing among the Top 10 of the most promising tech startups.
At our stand H4.2-E49 we showed sovereign Edge-AI live: a complete AI stack on our own hardware, powered by our NPU design Vexon-1, developed in Germany. Countless conversations with industry, investors and partners made clear how strong the demand is for data-sovereign AI without cloud dependency.
The real win was visibility: new contacts, leads and partnerships that we are now following up. Thanks to everyone who stopped by our stand.
May 19–20, 2026 · microTEC Clusterkonferenz
On 19 and 20 May 2026, NeuroVexon was present at the microTEC Clusterkonferenz. The Vexon-1 prototype ran live at the booth — the NPU block on an AMD Kria KV260 board, with our own edge-AI architecture of a RISC-V control core and a multi-tile NPU.
In many conversations with experts and potential partners we presented the five core innovations and the idea behind Vexon-1: sovereign AI starts at the silicon.
Serkan Bicen speaks in the start-up slot of the IT & AI Forum Ortenau (Offenburg University / microTEC Südwest) about edge AI right at the sensor: why kilohertz data rates force local processing and what an in-house NPU design has to deliver for it. Venue and registration details to follow.
We are glad to welcome Adrian Schenke to the team. As Senior Technical Lead he strengthens our consulting work in particular: a cloud and infrastructure engineer focused on automation and systems integration. He owns the automation and infrastructure side of our software stack and teaches as a co-instructor in our training courses.
Alongside the "AI System Owner (IHK)" certificate course, four day seminars are now bookable at the IHK-Bildungshaus of the IHK Region Stuttgart: "AI-Powered Process Optimization for Office & Procurement" (24+26 Nov 2026 / 16+18 Mar 2027) and "AI in the Public and Social Sector" (3+8 Dec 2026 / 20+22 Apr 2027) — two mornings each, 9:00–12:15.
Second FPGA platform, several NPU tiles in parallel, compute array twice the size, our own RISC-V sequencer with firmware — all proven bit-exact in hardware. Report with video and pictures above.
NeuroVexon reached the finals of the Supernova Pitch Competition at GITEX Europe 2026 and pitched on the Main Stage in Berlin — among the Top 10 of Europe's most promising tech startups. At stand H4.2-E49 we showed sovereign Edge-AI live on our own hardware. Report with photos and video above.
SUPERNOVA PITCH COMPETITION ↗For the first time, a real language model (TinyLlama-1.1B) generates tokens with the Vexon NPU in the data path — the FPGA as a correctness proof. Technology readiness level TRL 5 is confirmed, with a clear path to TRL 6 (Q3/2026).
The DMA data path runs bit-exact (256/256); the compute results match the reference bit-for-bit. Four of the five core innovations are reintegrated with the data path in a single bitstream — timing signoff at 100 MHz, reboot-persistent on the Kria KV260.
We showed the FPGA-verified Vexon-1 prototype live — with a demo of all five core innovations and many conversations with partners. See the report with photos above.
Sparse Attention Fusion, Adaptive Precision, and Hardware KV-Cache as three separate filings. Registration expected within 2–4 months.
9 of 9 tests reproducible on Xilinx Kria FPGA via REST API. Sparse Engine, Adaptive Precision, Multi-Tile, hardware attention, and KV-Cache hardware-proven.
More than 10,000 automated simulation checks in the Verilog stack successfully completed. Foundation for the FPGA integration.
Multi-tile compute active in parallel. First proof that the architecture scales on real hardware.